1. Technical Field
The present invention relates to a MOS-type (metal oxide semiconductor) semiconductor device such as an insulated gate field-effect transistor (MOSFET) or insulated gate bipolar transistor (IGBT), and a method for manufacturing the semiconductor device.
2. Background Art
A surface MOS structure of a power MOSFET, one of the conventional general MOS-type semiconductor devices, is now described. FIG. 4 is a cross-sectional diagram showing substantial parts of a surface MOS structure of a conventional MOSFET. FIG. 5 is a characteristic diagram showing a distribution of impurity concentrations in regions disposed along line A1-A2 in FIG. 4, the distribution being obtained when concentration compensation is not performed at a region boundary. FIG. 6 is a characteristic diagram showing a distribution of impurity concentrations in the regions disposed along line A1-A2 of FIG. 4, the distribution being obtained when concentration compensation is performed at a region boundary. FIG. 5 illustrates a concentration distribution of an impurity which is a dopant placed in each of the regions such as an n+-type source region 4, a channel forming region 10 within a p-type well region 3, and an n− layer configuring a semiconductor substrate, which are adjacent to one another along the line A1-A2 extending horizontally on the main surface, the surface layer of the semiconductor substrate having the surface MOS structure of the MOSFET shown in FIG. 4. FIG. 6 shows a net doping concentration distribution of a donor and an acceptor in each of the regions adjacent to one another along the line A1-A2. The numbers (reference numerals 4, 10, 2) described in an upper part of the frame of each of the graphs shown in FIGS. 5 and 6 represent the regions, which are denoted by the same reference numerals in FIG. 4, and FIGS. 5 and 6 show respectively an impurity concentration distribution and a doping concentration distribution of the regions corresponding to these numbers.
As shown in FIG. 4, the front surface side of the semiconductor substrate configuring an n− layer 2 has a surface MOS structure in which a gate electrode 7, made of polysilicon, is disposed on a surface of the channel forming region 10, with a gate insulator 6 therebetween, the channel forming region 10 being a part of the p-type well region 3 that is sandwiched between the n+-type source region 4 and the surface layer of an n− layer 2. ON/OFF control of the main current in the power MOSFET is performed by applying a voltage to the gate electrode 7 provided on the surface of the channel forming region 10 with the gate insulator 6 therebetween, and then inverting the conductivity type of the channel forming region 10 to the n-type. A gate threshold voltage of a general power MOSFET is set at approximately 1.0 V to 5.0 V. The thickness of the gate insulator 6 is set at approximately 500 to 1200 Å so that the gate threshold voltage in the abovementioned range is obtained.
In this surface MOS structure, because the length of the channel forming region 10 in the p-type well region 3 (the distance between the n+-type source region 4 and the surface layer of the n− layer 2 in the p-type well region 3, i.e., the distance in which the main current flows: channel length), the impurity concentration in the surface of the channel forming region 10, the film thickness of the gate insulator 6, and the like have a direct impact on the characteristics of an on-resistance and the characteristics of a gate threshold voltage, these components are the key components in designing the device. In other words, the channel forming region 10 is formed with care so that the main current flows evenly within an active part of the semiconductor substrate (chip) of the MOSFET and that the channel length, the surface impurity concentration and the like are kept balanced. The active part is a region in which the main current flows when the semiconductor device is in the ON state.
As a method for keeping the channel length balanced and forming each of the regions with high dimensional accuracy, there is known a method for forming each of the regions by self-alignment. A method for manufacturing (preparing) a conventional MOSFET in which the n+-type source region 4 is formed in the p-type well region 3 by self-alignment, is schematically described with reference to FIGS. 23 to 31. FIGS. 23 to 31 are cross-sectional diagrams of substantial parts of a semiconductor substrate, each showing sequentially the steps of manufacturing a surface MOS structure of a conventional MOSFET. FIGS. 23 to 31 are process drawings of cross sections of an element, showing a method for manufacturing a MOSFET according to Patent Document 1 (identified further on).
First, an insulator 31 on a front surface of an n-type silicon substrate 30 is patterned into a required opening for a p-type well region to form a mask for the insulator 31, and then a thin screen oxide film 32 is formed on the n-type silicon substrate 30. Then, masking with this mask for the insulator 31, p-type impurity ions are implanted through the screen oxide film 32 (FIG. 23). The p-type impurity is then diffused by heat, to form a p-type well region 33 on the surface layer of the n-type silicon substrate 30 (FIG. 24).
Next, a resist mask 34a having an open region for forming a p+ contact region is formed on the insulator 31 and the screen oxide film 32. Masking with the resist mask 34a, ion implantation 35 is carried out to implant boron (B) through the screen oxide film 32 (FIG. 25), to form a p+ contact region 36 inside the p-type well region 33 (FIG. 26). Subsequently, the resist mask 34a is removed. Thereafter, a resist mask 34b for forming an n+-type source region is formed on the screen oxide film 32, and an opening 39a is formed on the resist mask 34b to expose the area for forming an n+-type source region (FIG. 27).
Next, masking with the resist mask 34b and the insulator 31, arsenic (As) ions are implanted through the screen oxide film 32, and then the resist mask 34b is peeled off. The implanted arsenic ions are then annealed to form an n+-type source region 39 across a surface layer of the p-type well region 33 on the substrate front surface side and a surface layer of the p+ contact region 36 on the substrate front surface side (FIG. 28). With the use of the same mask for the insulator 31, the positional relationship between the p-type well region 33 and the n+-type source region 39 becomes constant due to self-alignment thereof.
Thereafter, the mask for the insulator 31 is removed (FIG. 29), and a gate insulator 37 is formed on the front surface of the n-type silicon substrate 30 by thermal oxidation (FIG. 30). A polysilicon film is formed on this gate insulator 37 and etched into a required pattern, to form the gate insulator 37 and a gate electrode 38 (FIG. 31). Thereafter, a general method is used to form remaining front surface element structures on the front surface of the n-type silicon substrate 30, such as an interlayer insulator and a source electrode (not shown), as well as a drain electrode (not shown) on the rear surface of the n-type silicon substrate 30. As a result, the conventional MOSFET is completed.
Another example of the method for manufacturing a conventional MOSFET is schematically described with reference to FIGS. 32 to 38, the method including a self-alignment step. FIGS. 32 to 38 are cross-sectional diagrams of substantial parts of a semiconductor substrate, each showing sequentially the other examples of steps of manufacturing a surface MOS structure of a conventional MOSFET. FIGS. 32 to 38 are process drawings of cross sections of an element, each showing a method for manufacturing a MOSFET according to Patent Document 2 (identified further on). First, a gate insulator is formed on the front surface of an n-type silicon substrate 30. Subsequently, a polysilicon film is formed on the gate insulator 37 and etched into a required pattern, thereby forming the gate insulator 37 and a gate electrode 38.
Masking with the gate electrode 38, boron ions are implanted through the gate insulator 37 (FIG. 32), to form a p-type well region 33 on a surface layer of the front surface of the n-type silicon substrate 30 (FIG. 33). This method for manufacturing a conventional MOSFET is different from the method for manufacturing a conventional MOSFET that is previously described, in that the p-type well region 33 is formed by masking with the gate electrode 38 that is formed prior to forming the p-type well region 33. Next, as shown in FIGS. 34 to 38, a p+ contact region 36 and an n+-type source region 39 are formed using the same steps as those of the previously described method for manufacturing a conventional MOSFET. As a result, a surface MOS structure is obtained. Reference numeral 34a shown in FIG. 34 represents a resist mask for forming the p+ contact region 36. Reference numeral 34b shown in FIG. 36 represents a resist mask for forming the n+-type source region 39.
This method for using the gate electrode 38 as a mask and forming the p-type well region 33 and the n+-type source region 39 by self-alignment is widely used in vertical MOS gate-type elements (MOS semiconductor devices). A vertical MOS gate-type element is an element that uses a MOS gate to control the current flowing vertically from one of the surfaces of a semiconductor substrate to the other surface. Examples of such an element include a power MOSFET and an insulated gate bipolar transistor (IGBT).
These two methods for manufacturing a surface MOS structure of a conventional MOSFET are common in that the p-type well region 33 and the n+-type source region 39 are formed by self-alignment. It is important to form the p-type well region 33 and the n+-type source region 39 by self-alignment in order to make the channel length (the distance in which the main current flows) uniform.
With regard to a gate threshold voltage, it is known that the film thickness of a gate insulator and the impurity concentration in a p-type well region have the following relationship. Reducing the impurity concentration in the surface of the p-type well region can reduce the impurity concentration in an area of the p-type well region in the vicinity of the n+-type source region where a channel is formed, resulting in reducing the gate threshold voltage. However, the risk in such a relationship is that conduction of a parasitic transistor is made easily during the ON state of the semiconductor device due to the reduced impurity concentration in the channel forming region, resulting in not being able to control the gate. In addition, because the p-type well region is formed by thermal diffusion, reducing the impurity concentration in the channel forming region can further lower the impurity concentration in a part of the p-type well region other than the channel forming region according to a Gaussian distribution. Consequently, a depletion layer easily expands in the p-type well region during the OFF state of the semiconductor device, which can result in damaging the semiconductor device by punch-through.
On the other hand, the thicker the film thickness of the gate insulator, the greater the gate threshold voltage. However, it is preferred that the gate insulator be thick in terms of improving dielectric breakdown withstand capability of the gate insulator itself (referred to as “gate breakdown withstand capability,” hereinafter) and reducing the gate capacity (i.e., reducing the switching loss). When the impurity concentration in the surface of the channel forming region is high, a high electric field (high gate threshold voltage) is required in order to reverse the conductivity type of the channel forming region upon application of a gate voltage. However, when the design range of the gate threshold voltage is restricted to approximately 1.0 V to 5.0 V as described above, the gate insulator cannot be made thicker than 1200 Å. Moreover, it is preferred that the gate threshold voltage be made low for the purpose of reducing dielectric breakdown of the gate insulator.
As a MOS semiconductor device that is configured to reduce the impurity concentration of a channel forming region in relation to a p-type well region (p-base region), there is proposed a power FET that has a surface-side region of a p-base region where a channel is formed and a lower region constituting the remaining part of the p-base region, wherein a gate threshold voltage is reduced while lowering the impact of a parasitic transistor, by reducing the impurity concentration in the surface-side region of the p-base region and increasing the impurity concentration in the lower region of the same (see Patent Document 3, identified further on, for example).
The following method is proposed as a method for reducing a gate capacity. Of the film thickness of a gate insulator, the film thickness of a part corresponding to the center of a semiconductor substrate region sandwiched between p-base regions is made as thick as 6000 Å, and the film thickness of the surrounding area is made as thin as 500 to 1200 Å. Masking with this gate insulator, a donor impurity is doped through the thin part of the gate insulator. In this manner, an n-type region that has an impurity concentration higher than that of the front surface of the semiconductor substrate is formed only below the thin part of the gate insulator, into a thickness greater than the thickness of a source region and a depth shallower than the depth of a p well region (see Patent Document 4, identified further on, for example).
As a method for adjusting a gate threshold voltage while preventing a depletion layer from being a punch-through state, there is proposed a method for forming a pocket region having a peak concentration higher than that of an n-type substrate region, between the n-type substrate region and a high-concentration p-type source region by implanting n-type impurity ions prior to forming a gate electrode and, prior to or after forming the high-concentration p-type source region by introducing a p-type impurity to an upper part of the n-type substrate region (see Patent Document 5, identified further on, for example). In Patent Document 5, ions of the same conductivity type as that of the n-type substrate region are implanted into a part of the n-type substrate region (well region) in the vicinity of the gate insulator, to selectively form a high-concentration region in contact with the source region and increase the gate threshold voltage.    Patent Document 1: Japanese Patent Application Publication No. H6-244428    Patent Document 2: Japanese Patent Application Publication No. H6-5865    Patent Document 3: Japanese Translation of PCT Application No. H6-504882    Patent Document 4: Japanese Patent Application Publication No. H4-125972    Patent Document 5: Japanese Patent Application Publication No. 2005-229066
As described previously, the film thickness of a gate insulator of a MOSFET and the impurity concentration in a p-type well region are in a trade-off relationship with respect to a gate threshold voltage. In addition, increasing the film thickness of the gate insulator of the MOSFET can help improve the gate breakdown withstand capability and reduce the gate capacitance.
Although increasing the film thickness of the gate insulator increases a gate threshold voltage as described above, there is a limit to increasing the film thickness of the gate insulator. Furthermore, the gate threshold voltage of the MOSFET is determined based on the film thickness of the gate insulator and the impurity concentration in the surface of the channel forming region located outside the n+-type source region inside the p-type well region. In addition, since the channel forming region configures a current path for the main current, the p-type well region and the n+-type source region are formed by self-alignment so that the distance therebetween (channel length) becomes constant in order to keep the resistance constant in the current path in the conventional methods described in Patent Documents 1 to 5.
In the channel forming region 10 of the conventional MOSFET formed by these methods (FIG. 4), the distribution of impurity concentrations in the p-type well region 3 and the n+-type source region 4 has an inclination where the impurity concentrations gradually decrease in accordance with the depth of the semiconductor substrate from the ion implantation region (surface) on the front surface side of the substrate. In this case, the gate threshold voltage is determined based on the impurity concentration in the surface of the p-type well region 3 in the vicinity of the joint between the p-type well region 3 and the n+-type source region 4.
Therefore, even when the film thickness of the gate insulator is increased, increase of the gate threshold voltage can be suppressed by reducing the impurity concentration in the surface of the p-type well region in the vicinity of the joint between the p-type well region 3 and the n+-type source region 4. However, the impurity concentration in the surface of the p-type well region is closely related to the withstand voltage and on-resistance of the semiconductor device, there is no choice but setting the impurity concentration within a range not affecting the withstand voltage and on-resistance negatively. For this reason, there is a limit to a lower limit of the gate threshold voltage that can be adjusted by reducing the impurity concentration in the surface of the p-type well region, as well as to increasing the film thickness of the gate insulator determined based on the gate threshold voltage. In Patent Document 5, the gate threshold voltage can only be increased because the gate threshold voltage is adjusted by forming a high-concentration region in the well region by implanting ions of the same conductivity type as that of the well region. Another problem with Patent Document 5 is that reducing the impurity concentration in the p-type well region allows a depletion layer to spread, consequently causes a short channel effect, and enables operation of a parasitic bipolar transistor.